library ieee;
use ieee.std_logic_1164.all;

entity register_n is
    generic (
        N        : integer := 4
    );
    port (
        clk_i 	 : in  std_logic;
        nreset_i : in  std_logic;
        we_i	 : in  std_logic;
        d_i      : in  std_logic_vector(N-1 downto 0);
        q_o      : out std_logic_vector(N-1 downto 0)
    );
end register_n;

architecture behav of register_n is
begin
    process(clk_i)
        begin
        if (clk_i = '1' and clk_i'event) then
            if(nreset_i = '0') then
                q_o <= (others => '0');
            elsif(we_i = '1') then
                q_o <= d_i;
            end if;
        end if;
    end process;
end behav;
